Power consumption can affect computational performance of microprocessors and systems-on-chip. Battery life, energy costs, and maximum operating temperature can each impose a power envelope on digital ICs that is generally mitigated by throttling computational performance. As such, performance-per-watt can be a useful metric for comparing energy efficiency of a processor. Dynamic voltage and frequency scaling (DVFS) can provide improved performance-per-watt by reducing supply voltages during periods of low computational demand, but implementations can be improved by reducing the time scales over which the supply voltage is positioned, allowing real-time adjustment of power consumption in the presence of workload variability. For the case of chip multiprocessors and heterogeneous systems-on-chip (SoCs), computational logic can be generally divided into individual voltage-frequency domains, allowing per-core or per-functional-block DVFS. Generally, a DVFS implementation with faster voltage transition times and smaller voltage-frequency domains delivers a relatively more energy-efficient implementation. However, some methods for power supply regulation with board-level voltage regulator modules (VRM) can require tens of microseconds to transition voltages and can be too bulky to deliver many independent power supplies in a cost effective manner.
External VRMs can present other efficiency challenges. For example, I2R losses in the power distribution network (PDN) can be significant when relatively highly-scaled voltages are delivered from the board. In certain PDNs, a resistance from the VRM to the CPU's package of 0.7 mΩ can dissipate 7 W of power for 100 W load at 1 V. Further, VRMs utilize power supply margins that can degrade energy efficiency. The high-frequency impedance of the PDN can inhibit the VRM's ability to suppress voltage overshoot in the event of load current transients. As such, VRM specifications can stipulate that the supply voltage follow a load-line represented as vOUT=VZL−RLLiO, where vOUT represents the processor supply voltage, VZL represents the desired vOUT at zero load, RLL represents the desired load-line resistance, and iO represents the load current. Implementation of load-line control can reduce the VRM size and cost required to maintain the output voltage within the allowed tolerance during load transients. However, for example when the system is not operating at maximum power consumption, the load-line can be a source of inefficiency as υOUT can be greater than the minimum supply voltage, VMIN=VZL−RLLIO,MAX, where IO,MAX represents the maximum load current. The wasted power can be represented as PLL=iORLL(IO,MAX−iO). For a value for RLL of 1 mΩ, a CPU with IO,MAX of 100 A operating at 50 A and 1 V can waste 2.5 W in the load-line implementation. If the PDN impedance were smaller, the value of RLL and hence the load-line inefficiency could be reduced.
Switch-mode integrated voltage regulators (IVRs) can be utilized to address these challenges in VRMs. For example, energy can be stored on or close to the integrated circuit in capacitors (switched-capacitor converters) or inductors (buck converters). Integrated switched-capacitor converters, which can take advantage of high-density integrated capacitors, can have relatively high efficiency at reasonable current densities, but at a fixed conversion ratio and without addressing transient requirements. Meanwhile, integrated buck converters can have high current densities and efficiencies with a continuous range of conversion ratios, but can be challenging to integrate with high-quality inductors.
Planar spiral or other inductor topologies that can be constructed using the interconnects of a typical CMOS process can be too resistive to provide efficient on-chip power conversion at reasonable current densities. Surface mount technology (SMT) air-core inductors, which can provide a current density up to ˜1.7 A/mm2, can be utilized. However, the size and discrete nature of these devices can hinder the scalability of IVRs incorporating discrete SMT inductors. Nevertheless, some integrated magnetic-core power inductors can be relatively highly scalable and capable of delivering current densities up to 8 A/mm2 or more. These inductors can be included in IVR prototypes by on-chip integration and chip stacking, which can provide highly scalable and efficient switched-inductor IVRs.
Another issue in the development of switched-inductor IVRs can be the integration of decoupling capacitance. While VRMs can generally augment voltage regulation at high frequencies by leveraging large amounts of inexpensive board-level decoupling capacitance, the integrated capacitance utilized in IVRs can be much greater. In switched-inductor IVRs, decoupling capacitance can be determined to suppress voltage overshoot during fast load current transients. Extending the IVR controller bandwidth can reduce these decoupling capacitance effects.
Some switched-inductor IVRs can address transient response by utilizing a multi-phase hysteretic controller to provide nearly instantaneous response to transients, which can effectively reduce the required output decoupling capacitance. However, the closed loop behavior of the multi-phase hysteretic controller can be difficult to predict and can have loose synchronization of phases producing an under-damped large-signal response. Also, certain hysteretic controllers do not operate at fixed switching frequency, and can therefore pose challenges when attempting to control EMI. Pulse-width modulation (PWM) controllers can be utilized, which can compensate for increased controller delay using abundant package-level decoupling capacitance. However, the package-level capacitance can increase component and packaging cost and reduce scalability.